Known ferroelectric random access memories (FRAM) are constructed using one transistor and one capacitor. The capacitor is generally made by sandwiching a thin ferroelectric (FE) film between two conductive electrodes, which electrodes are usually made of platinum, or an alloy thereof. The circuit configuration in the read/write sequence of this type of memory is similar to that of conventional dynamic random access memories, except that no data refreshing is required in a FRAM. Known FRAMs, however, have a fatigue problem that has been observed in the ferroelectric capacitor, which is one of the major obstacles that limit the viable commercial use of such memories. The fatigue is the result of a decrease in the switchable polarization (stored nonvolatile charge) that occurs with an increased number of switching cycles. As used in this case, "switching cycles" refers to the sum of erasing and writing pulses in the memory.
The foregoing problems have been resolved, and such resolution is set forth in pending U.S. patent applications and patents identified above. In those applications and patents, however, at the time of filing same, the process for manufacturing included conventional etching and polishing of the FE memory cells. Although the memory devices made by such processes are superior to those made according to the known art at the time, problems may arise due to short circuits being caused by residual metal particles from the conductive electrodes of the capacitor contaminating the FE material and the surrounding oxides. Additionally, dry etching of FE thin films caused the electrical characteristics of those films to deteriorate. Because of the problem with metal particles causing short circuits, it is necessary to space the devices apart on the wafer and to maintain a certain size thereto, in order to keep the capacitors therein at a relatively large size. The disclosure herein provides a method to eliminate the aforementioned problems.